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NCP561 150 mA CMOS Low Iq Low-Dropout Voltage Regulator
The NCP561 series of fixed output low dropout linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent. The NCP561 series features an ultralow quiescent current of 3.0 mA. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits. The NCP561 has been designed to be used with low cost ceramic capacitors and requires a minimum output capacitor of 1.0 mF. The device is housed in the micro-miniature TSOP-5 surface mount package. Standard voltage versions are 1.5 V, 1.8 V, 2.5 V, 2.7 V, 2.8 V, 3.0 V, 3.3 V and 5.0 V.
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5 1 TSOP-5 SN SUFFIX CASE 483
PIN CONNECTIONS AND MARKING DIAGRAM
VIN GND Enable 1 xxxYW 2 3 (Top View) xxx = Specific Device Code Y = Year W = Work Week 5 VOUT
* * * * * *
Low Quiescent Current of 3.0 mA Typical Low Dropout Voltage of 170 mV at 150 mA Low Output Voltage Option Output Voltage Accuracy of 2.0% Industrial Temperature Range of -40C to 85C Pb-Free Packages are Available
4 N/C
Typical Applications
* Battery Powered Instruments * Hand-Held Instruments * Camcorders and Cameras
VIN 1 Thermal Shutdown Driver w/ Current Limit 5 VOUT
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
Enable ON OFF 3
GND
2
This device contains 28 active transistors
Figure 1. Representative Block Diagram
(c) Semiconductor Components Industries, LLC, 2004
1
July, 2004 - Rev. 4
Publication Order Number: NCP561/D
NCP561
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PIN FUNCTION DESCRIPTION
Pin No. 1 2 3 4 5 Pin Name VIN Description Positive power supply input voltage. Power supply ground. GND Enable N/C This input is used to place the device into low-power standby. When this input is pulled low, the device is disabled. If this function is not used, Enable should be connected to VIN. No internal connection. VOUT Regulated output voltage.
MAXIMUM RATINGS
Rating Input Voltage
Symbol VIN
Value 6.0
Unit V V V
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Enable Voltage Output Voltage Enable VOUT PD RqJA TJ -0.3 to VIN +0.3 -0.3 to VIN +0.3 Power Dissipation and Thermal Characteristics Power Dissipation Thermal Resistance, Junction-to-Ambient Operating Junction Temperature Operating Ambient Temperature Storage Temperature Internally Limited 250 +125 W C/W C C C TA -40 to +85 Tstg -55 to +150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL-STD-883, Method 3015 Machine Model Method 200 V 2. Latchup capability (85C) "100 mA DC with trigger voltage.
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NCP561
ELECTRICAL CHARACTERISTICS (VIN = VOUT(nom) + 1.0 V, Venable = VIN, CIN = 1.0 mF, COUT = 1.0 mF, TJ = 25C,
unless otherwise noted.) Characteristic Output Voltage (TA = 25C, IOUT = 1.0 mA) 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V Line Regulation 1.5 V-4.4 V (VIN = Vo(nom) + 1.0 V to 6.0 V) 4.5 V-5.0 V (VIN = 5.5 V to 6.0 V) Load Regulation (IOUT = 10 mA to 150 mA) Output Current (VOUT = (VOUT at Iout = 150 mA) -3.0%) 1.5 V to 3.9 V (VIN = Vo(nom) + 2.0 V) 4.0 V to 5.0 V (VIN = 6.0 V) Dropout Voltage (TA = -40C to 85C, IOUT = 150 mA, Measured at VOUT - 3.0%) 1.5 V - 1.7 V 1.8 V - 2.4 V 2.5 V - 2.7 V 2.8 V - 3.2 V 3.3 V - 4.9 V 5.0 V Quiescent Current (Enable Input = 0 V) (Enable Input = VIN, IOUT = 1.0 mA to Io(nom)) Output Short Circuit Current 1.5 V to 3.9 V (VIN = Vo(nom) + 2.0 V) 4.0 V to 5.0 V (VIN = 6.0 V) Output Voltage Noise (f = 20 Hz to 100 kHz, VOUT = 3.0, V IOUT = 1.0 V) Enable Input Threshold Voltage (Voltage Increasing, Output Turns On, Logic High) (Voltage Decreasing, Output Turns Off, Logic Low) Output Voltage Temperature Coefficient 3. Maximum package power dissipation limits must be observed. T *TA PD + J(max) RqJA 4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. Symbol VOUT 1.455 1.746 2.425 2.646 2.744 2.940 2.234 4.90 Regline - - Regload Io(nom) 150 150 VIN-VOUT - - - - - - IQ - - IOUT(max) 160 160 Vn Vth(en) 1.3 - TC - - - "100 - 0.2 - ppm/C - 400 400 60 800 800 - mVrms V 0.1 4.0 1.0 8.0 mA 330 240 150 140 130 120 500 360 250 230 200 190 mA - - - - mV - 10 10 30 20 20 60 mV mA 1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0 1.545 1.854 2.575 2.754 2.856 3.060 3.366 5.10 mV Min Typ Max Unit V
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NCP561
TYPICAL CHARACTERISTICS
VIN - VOUT, DROPOUT VOLTAGE (mV)
180 VOUT, OUTPUT VOLTAGE (V) 160 140 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 125 50 mA Load 100 mA Load 150 mA Load VOUT = 3.0 V
3.015 3.010 3.005 3.000 2.995 2.990 2.985 2.980 2.975 -50 0 50 100 VIN = 4.0 V IOUT = 10 mA
VIN = 6.0 V
TEMPERATURE (C)
TEMPERATURE (C)
Figure 2. Dropout Voltage vs. Temperature
4.75 Iq, QUIESCENT CURRENT (mA) 4.50 4.25 4.00 3.75 3.50 3.25 3.00 -50 0 50 100 Iq, QUIESCENT CURRENT (mA) IOUT = 10 mA VIN = 4.0 V 4.5 4.0 3.5 3.0 2.5 2.0 1.5
Figure 3. Output Voltages vs. Temperature
VOUT = 3.0 V IOUT = 0 mA TA = 25C
0
1
2
3
4
5
6
TEMPERATURE (C)
TEMPERATURE (C)
Figure 4. Quiescent Current vs. Temperature
5.0 IGND, GROUND PIN CURRENT (mA) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 0 1 2 3 4 5 6 VOUT = 3.0 V IOUT = 50 mA TA = 25C 4.0 OUTPUT NOISE VOLTAGE (mV/ Hz) 3.5 3.0 2.5 2.0 1.5 1.0 0.5
Figure 5. Quiescent Current vs. Input Voltage
1.0 mA
150 mA
0 10
100
1k
10 k
100 k
1000 k
VIN, INPUT VOLTAGE (V)
NOISE CHARACTERIZATION
Figure 6. Ground Current vs. Input Voltage
Figure 7. Output Noise Voltage
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NCP561
TYPICAL CHARACTERISTICS
VIN, INPUT VOLTAGE (mV)
CHANGE IN OUTPUT VOLTAGE (mV)
60 50 40
0 -50 -100 -150 -200 -250 VIN = 4.0 V VOUT = 3.0 V CIN = 1.0 mF COUT = 10 mF Al. Elec. Surface Mount
CHANGE IN OUTPUT VOLTAGE (mV)
400 200 0
IOUT = 10 mA COUT = 1.0 mF
IOUT, OUTPUT CURRENT (mA)
150 100 50 0 0 200 400 600 TIME (ms) 800 1000 1200
-200 -400 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 TIME (ms) 1.6 1.8 2.0
Figure 8. Line Transient Response
4 2 0 3 2 1 0 0 200 400 600 TIME (ms) 800 1000 1200 0
Figure 9. Load Transient Response
CHANGE IN OUTPUT VOLTAGE (mV)
0 -50 -100 -150 -200 -250 VIN = 4.0 V VOUT = 3.0 V CIN = 1.0 mF COUT = 10 mF Tantalum
VOUT, OUTPUT VOLTAGE (V)
ENABLE VOLTAGE (V)
IOUT, OUTPUT CURRENT (mA)
150 100 50 0
CIN = 1.0 mF COUT = 1.0 mF IOUT = 10 mA
200
400
600 800 1000 1200 1400 1600 TIME (ms)
Figure 10. Load Transient Response
3.5 VOUT, OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 4 VIN, INPUT VOLTAGE (V) 5
Figure 11. Turn-On Response
CIN = 1.0 mF COUT = 1.0 mF TA = 25C VENABLE = VIN
6
Figure 12. Output Voltage vs. Input Voltage
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NCP561
DEFINITIONS
Load Regulation Line Regulation
The change in output voltage for a change in output current at a constant temperature.
Dropout Voltage
The input/output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 3.0% below its nominal. The junction temperature, load current, and minimum input supply requirements affect the dropout level.
Maximum Power Dissipation
The change in output voltage for a change in input voltage. The measurement is made under conditions of low dissipation or by using pulse technique such that the average chip temperature is not significantly affected.
Line Transient Response
Typical over and undershoot response when input voltage is excited with a given slope.
Thermal Protection
The maximum total dissipation for which the regulator will operate within its specifications.
Quiescent Current
The quiescent current is the current which flows through the ground when the LDO operates without a load on its output: internal IC operation, bias, etc. When the LDO becomes loaded, this term is called the Ground current. It is actually the difference between the input current (measured through the LDO input pin) and the output current.
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated at typically 160C, the regulator turns off. This feature is provided to prevent failures from accidental overheating.
Maximum Package Power Dissipation
The maximum power package dissipation is the power dissipation level at which the junction temperature reaches its maximum operating value, i.e. 125C. Depending on the ambient power dissipation and thus the maximum available output current.
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NCP561
APPLICATIONS INFORMATION A typical application circuit for the NCP561 series is shown in Figure 13.
Input Decoupling (C1) Thermal
A 1.0 mF capacitor either ceramic or tantalum is recommended and should be connected close to the NCP561 package. Higher values and lower ESR will improve the overall line transient response. TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K
Output Decoupling (C2)
The NCP561 is a stable Regulator and does not require any specific Equivalent Series Resistance (ESR) or a minimum output current. Capacitors exhibiting ESRs ranging from a few mW up to 3.0 W can thus safely be used. The minimum decoupling value is 1.0 mF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response. TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K, or C3216X7R1C105K
Enable Operation
As power across the NCP561 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material and also the ambient temperature effect the rate of temperature rise for the part. This is stating that when the NCP561 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power dissipation applications. The maximum dissipation the package can handle is given by:
T *TA PD + J(max) RqJA
If junction temperature is not allowed above the maximum 125C, then the NCP561 can dissipate up to 400 mW @ 25C. The power dissipated by the NCP561 can be calculated from the following equation:
Ptot + [Vin * Ignd (Iout)] ) [Vin * Vout] * Iout
or
) VOUT * IOUT P VINMAX + TOT IGND ) IOUT
The enable pin will turn on the regulator when pulled high and turn off the regulator when pulled low. These limits of threshold are covered in the electrical specification section of this data sheet. If the enable is not used then the pin should be connected to VIN.
Hints
If a 150 mA output current is needed then the ground current from the data sheet is 4.0 mA. For an NCP561SN30T1 (3.0 V), the maximum input voltage will then be 5.6 V.
Battery or Unregulated Voltage 1 2 ON OFF 3 4 5 + VOUT C2
Please be sure the VIN and GND lines are sufficiently wide. When the impedance of these lines is high, there is a chance to pick up noise or cause the regulator to malfunction. Set external components, especially the output capacitor, as close as possible to the circuit, and make leads a short as possible.
C1
+
Figure 13. Typical Application Circuit
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NCP561
APPLICATION CIRCUITS
Input R
Q1
Input Q2
R1 R2 R3
Q1
Output 1 1.0 mF 2 3 4 5 1.0 mF
Output 1 5 1.0 mF 4
1.0 mF
2 3
Figure 14. Current Boost Regulator
The NCP561 series can be current boosted with a PNP transistor. Resistor R in conjunction with VBE of the PNP determines when the pass transistor begins conducting; this circuit is not short circuit proof. Input/Output differential voltage minimum is increased by VBE of the pass resistor.
Figure 15. Current Boost Regulator with Short Circuit Limit
Short circuit current limit is essentially set by the VBE of Q2 and R1. ISC = ((VBEQ2 - ib * R2) / R1) + IO(max) Regulator
Input 1 1.0 mF 2 Enable 3 4 5
Output 1.0 mF
Input Output 1 1.0 mF 2 5 1.0 mF R
Q1 1.0 mF 5.6 V
Output 1 2 3 4 5 1.0 mF
3 R C
4
Figure 16. Delayed Turn-on
If a delayed turn-on is needed during power up of several voltages then the above schematic can be used. Resistor R, and capacitor C, will delay the turn-on of the bottom regulator.
Figure 17. Input Voltages Greater than 6.0 V
A regulated output can be achieved with input voltages that exceed the 6.0 V maximum rating of the NCP561 series with the addition of a simple pre-regulator circuit. Care must be taken to prevent Q1 from overheating when the regulated output (VOUT) is shorted to GND.
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NCP561
ORDERING INFORMATION
Device NCP561SN15T1 NCP561SN18T1 NCP561SN25T1 NCP561SN25T1G NCP561SN27T1 NCP561SN28T1 NCP561SN28T1G NCP561SN30T1 NCP561SN33T1 NCP561SN50T1 Nominal Output Voltage 1.5 1.8 2.5 2.5 2.7 2.8 2.8 3.0 3.3 5.0 Marking LDA LEV LDC LDC LEX LDD LDD LDE LDF LDH Package TSOP-5 TSOP-5 TSOP-5 TSOP-5 (Pb-Free) TSOP-5 TSOP-5 TSOP-5 (Pb-Free) TSOP-5 TSOP-5 TSOP-5 3000 / 7 Tape & Reel Shipping
NOTE: Additional voltages are available upon request by contacting your ON Semiconductor representative. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCP561
PACKAGE DIMENSIONS
TSOP-5 (SOT23-5, SC59-5) SN SUFFIX PLASTIC PACKAGE CASE 483-02 ISSUE C
D
5 1 2 4 3
S
B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. A AND B DIMENSIONS DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 2.90 3.10 0.1142 0.1220 B 1.30 1.70 0.0512 0.0669 C 0.90 1.10 0.0354 0.0433 D 0.25 0.50 0.0098 0.0197 G 0.85 1.05 0.0335 0.0413 H 0.013 0.100 0.0005 0.0040 J 0.10 0.26 0.0040 0.0102 K 0.20 0.60 0.0079 0.0236 L 1.25 1.55 0.0493 0.0610 M 0_ 10 _ 0_ 10 _ S 2.50 3.00 0.0985 0.1181
L G A J C 0.05 (0.002) H K M
SOLDERING FOOTPRINT*
1.9 0.074
0.95 0.037
2.4 0.094 1.0 0.039 0.7 0.028
SCALE 10:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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NCP561/D

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